1. Technical Field
The present invention relates to a multi chip package.
2. Description of the Related Art
Recently, with the development of a semiconductor industry and the increase in user demand, a demand for small and light electronic devices has increased. One of the technologies applied to satisfy the demands is a multi chip packaging technology. The multi chip packaging technology is a technology of configuring a plurality of semiconductor chips into a single package. Using the multi chip package configured by the multi chip packaging technology is more advantageous in miniaturization, lightness, and a mounting area, as compared with using several packages including a single semiconductor chip.
An example of the multi chip packaging technology may include a method of stacking a plurality of semiconductor chips and a method of arraying a plurality of semiconductor chips in parallel. The former has a structure of stacking the semiconductor chips, such that it can reduce the mounting area and the latter has a structure of arraying the plurality of semiconductor chips on a plane, such that it simplifies a manufacturing process and is advantageous in terms of thickness. Recently, the multi chip package is used for a package requiring miniaturization and lightness. As a result, various ways of stacking the semiconductor chips has been introduced. Among the stacking methods of the multi chip packages, the multi chip package having two semiconductor chips mounted on a lead frame is referred to as a dual die package (DDP) type semiconductor chip package.
FIG. 1 is a cross-sectional view showing a dual die package according to the prior art. As shown in FIG. 1, a center pad type first semiconductor chip 300 is attached to a printed circuit board 100 having a cavity formed at a central portion thereof in a face-down manner by an adhesive 200 and a center pad type second semiconductor type 600 is attached to the bottom surface of the first semiconductor chip 300 in a face-up manner by an adhesive 400. A bonding pad (not shown) of the first semiconductor chip 300 is electrically connected to a circuit pattern (not shown) on the bottom surface of the printed circuit board 100 by a first metal wire 500 penetrating through the cavity of the printed circuit board 100 and a bonding pad (not shown) of the second semiconductor chip 600 is electrically connected to an electrode terminal 120 on the top surface of the printed circuit board 100 by a second metal wire 700.
In addition, the top surface of the printed circuit board 100 including the first semiconductor chip 300, the second semiconductor chip 600, and the second metal wire 700 and the cavity portion of the printed circuit board 100 including the first metal wire 500 and a portion of the entire surface of the first semiconductor chip 300 are sealed with a sealant 900 such as EMC and ball lands 130 mounted on the bottom surface of the printed circuit board 100 are attached with solder balls 140 as a mounting member.
In the case of the dual die package according to the prior art, a structural difference in the lengths of the first metal wire and the second metal wire of each of the first semiconductor chip and the second semiconductor chip occurs. The first semiconductor chip having a relatively short transmission line transmits signals faster than the second semiconductor chip. This causes signal distortions such as stress, etc., occurring at the time of power delivery. Further, there are problems of degradation of electrical characteristics of the dual die package and degradation of operation reliability of the package due to the signal distortions. In addition, even in the case of two or more multi chip packages as well as the dual die package, signal distortions occur due to the difference in the lengths of the metal wires for electrically connecting each semiconductor chip.